FIG. 16 is a diagram illustrating an example of a conventional operation system that temporarily stores data in a buffer memory to perform processing.
The conventional clock control type processor can control supply and stop of a clock by the processor itself, without requiring control by an external microcomputer or the like.
In FIG. 16, a buffer memory 11 is constituted by a high-capacity memory element such as a DRAM. This buffer memory 11 is divided into plural areas, each corresponding to a block which is subjected to processing such as error correction for a DVD, and one address is allocated to one block. There are three kinds of operations in which accesses to the buffer memory are made, i.e., a writing operation, a processing operation, and a reading operation, and the accesses are made by a writing control circuit 12, a processing circuit 13, and a reading control circuit 14, respectively. An address generation circuit 15 controls an address at which the access to the buffer memory 11 is made by these accessing systems, respectively, to perform control for avoiding an overflow or underflow in the buffer memory 11, and makes the buffer memory 11 carry out a ring operation. In this ring operation for example, the address is successively incremented by “1” from the minimum value of the address (“0”), then returned to “0” after reaching its maximum value “n+1” (n is 0 or a positive integer), and thereafter the same operation is repeated. A clock control circuit 16 generates an operation clock 102 for the processing circuit 13 under the control of a basic clock 101. The clock control circuit 16 can activate the operation clock 102 in accordance with a writing completion signal 103 from the writing control circuit 12, and stop the operation clock 102 in accordance with a processing end signal 104 from the processing circuit 13.
FIG. 17 is a diagram specifically illustrating a structure of the clock control circuit 16 in FIG. 16.
In FIG. 17, the clock control circuit 16 receives the basic clock 101, and generates the operation clock 102 that is supplied to a control target. At this time, the writing completion signal 103 is inputted through an operation signal line 16a and the processing end signal 104 is inputted through a stop signal line 16b, to a R-S flipflop 18 in the clock control circuit 16, respectively. When the R-S flipflop 18 gets into a set state in accordance with the writing completion signal 103, the basic clock 101 is passed through an AND circuit 19, and then the operation clock 102 is supplied. Thereafter, the processing end signal 104 is inputted, and then the R-S flipflop 18 gets into a reset state, whereby the supply of the operation clock 102 is stopped by the AND circuit 19. The supply of the clock is resumed in accordance with the next writing completion signal 103.
FIG. 18 is a timing chart for explaining the prior art as shown in FIG. 16.
As shown in FIG. 18, the writing control circuit 12 writes inputted data 106 at an address in the buffer memory 11, specified by the address generation circuit 15. When the writing corresponding to one block in the memory area is completed, the writing control circuit 12 outputs the writing complete signal 103, and writes data in the next block area. The processing circuit 13 subjects the data corresponding to one block, which have already been written into the memory, to processing. When predetermined processing is finished, the processing circuit 13 outputs the processing end signal 104 to make the clock control circuit 16 stop the operation clock 102 for the processing circuit 13. Thereafter, the operation clock 102 is stopped during a period in which the processing circuit 13 does not perform processing until it is activated by the writing completion signal 103 for the next block, thereby reducing power consumption.
In the operation of the conventional clock control type processor, it is premised that a processing time in the processing circuit is shorter than a time of writing corresponding to one block at an approximately constant input rate. When this premise is met, the processing circuit is kept in a waiting state until writing of the next block is completed, and the operation clock for the processing circuit is stopped during this time, thereby reducing power consumption.
However, in the conventional operation system, there is no guarantee that the writing time, the reading time, and the processing time are fixed. For example, in a case where this system is applied to a DVD decoder, the writing time varies with the rate of inputted data, and the processing time varies with the contents of the data. Further, when the buffer memory is heavily accessed, the operating speed of each accessing system greatly varies with the access priority.
FIG. 19 is a timing chart for explaining the structure according to the prior art shown in FIG. 16, like in FIG. 18, and shows a behavior when the processing time corresponding to one block gets longer. In this case, FIG. 19 shows a state in which the processing of one block takes a time that is longer than the writing time corresponding thereto.
According to the prior art structure in which the clock control circuit 16 that generates an operation clock in accordance with the basic clock is stopped by the processing end signal 104 and activated by the writing completion signal 103, the clock operation is not changed by the writing completion signal 103 that is outputted before the processing end signal 104 and the operation clock is kept in the operating state, but unfavorably stopped by the processing end signal 104 that is outputted later. That is, the clock is stopped although the circuit is not in a waiting state but there are blocks which are to be successively processed, and further the clock is returned after waiting for the writing completion signal 103 for the next block to resume the processing. When the processing takes a long time, an address of a block to be written (hereinafter, referred to as a writing block address) and an address of a block to be processed (hereinafter, referred to as a processing block address) are away from each other, and the difference between these addresses cannot be recovered. Accordingly, the margin in the buffer memory is gradually reduced every time when the processing takes a longer time.